Assess students' understanding of CPU pipelining hazards—structural, data, and control—by asking them to identify and classify hazards in short instruction sequences, explain causes and effects on pipeline timing (stalls, bubbles), compute or illustrate required stall cycles or use of forwarding, and evaluate common mitigation techniques (forwarding, stalling, register renaming, branch prediction, delayed branching, speculative execution, scoreboarding/Tomasulo) including trade-offs in complexity and performance; suitable for undergraduate, medium-difficulty assessment focused on comprehension and analysis.