Assess students' ability to design and implement a simplified 5-stage pipelined RISC‑V–compatible CPU: define a compact ISA and binary encodings, implement an assembler that emits machine code, and build a cycle-accurate IF/ID/EX/MEM/WB simulator. The assessment focuses on correctness of encodings, assembler output, and simulator behavior including data-hazard resolution (forwarding/stalls), control-hazard handling (branch prediction strategies and flushes), and basic exception handling (illegal instructions, memory faults). Deliverables: ISA spec, assembler, simulator, test programs and cycle-by-cycle traces.